This invention relates to programmable logic devices having blocks that perform multiplication and other arithmetic functions. More particularly, this invention relates to a method for programming such programmable logic devices while taking into account constraints imposed by those blocks or by users.
Programmable logic devices are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved by “blowing”—i.e., opening—fusible links. Alternatively, the configuration may have been stored in a programmable read-only memory. Those devices generally provided the user with the ability to configure the devices for “sum-of-products” (or “P-TERM”) logic operations. Later, such programmable logic devices incorporating erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which also can be reconfigured, store their configuration in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provide the user with the ability to configure the devices for look-up-table-type logic operations. At some point, such devices began to be provided with embedded blocks of random access memory that could be configured by the user to act as random access memory, read-only memory, or logic (such as P-TERM logic).
As programmable logic devices have become larger, it has become more common to add dedicated multiplier circuits on the programmable logic devices. Whereas in prior programmable logic devices space was not available for dedicated multipliers, current larger devices can accommodate multipliers. This spares users from having to create multipliers by configuring the available logic. Moreover, as described in copending, commonly-assigned U.S. patent application Ser. No. 09/955,645, filed Sep. 18, 2001, specialized multiplier blocks may be provided including multipliers and other arithmetic circuits such as adders and/or subtracters and/or accumulators. Such blocks are sometimes referred to as “multiplier-accumulator blocks” or “MAC blocks.” Such blocks, for example, may be useful in digital signal processing, such as is performed in audio applications, and therefore such specialized multiplier blocks also are sometimes referred to as “DSP blocks.”
While it may have been possible to program the earliest programmable logic devices manually, simply by determining mentally where various elements should be laid out, it was common even in connection with such earlier devices to provide programming software that allowed a user to lay out logic as desired and then translate that logic into programming for the programmable logic device. With current larger devices, it would be impractical to attempt to lay out the logic without such software.
The aforementioned specialized multiplier blocks present issues that had not existed in prior generations of programmable logic devices. In particular, because such blocks are large and complex, the number of such blocks on any one device may be relatively small, and they are placed in specific locations. Therefore, any programming software or method used with such devices must be able to implement a user logic design that incorporates the specialized multiplier blocks, including obeying the constraints imposed by those blocks or by the user, as well as by the relative location of those blocks to other logic regions with which they must interact.